Demand for semiconductors, wafers, integrated circuits and semiconductor devices (i.e., collectively “semiconductors”) continues to rapidly increase. With the continued market demand, there remain market pressures to increase the number of wafers that can be processed, reduce the geometries of finished wafers and their associated chip footprints, and increase component counts in the reduced geometries. Being able to sustain and meet the market demands with a reliable and consistent offering is a challenge however, in part because wafer manufacture is an environment that is both process sensitive and equipment intensive.
The fabrication of wafers (i.e., fabrication, fab, or fab environment) requires advanced processing equipment, unique toolings and extensive research efforts. Process tools (i.e., toolings) in these environments may often run in parallel or have multiple components to produce similar products (i.e., yields or outputs). Yet these same process tools, even when of the same manufacturer or source, may have unique variances in their individual performances which may create substantial or measurable differences in the quality of the products produced if unaccounted for.
A process tool may include a furnace, a furnace having a plurality of chambers, a furnace bank, a furnace tube, a processing chamber in which a wafer is acted upon, a processing activity point in a fab line where a wafer may be received or acted upon, and the like. In other aspects, a process tool may further include a controller or control mechanism for controlling a process tool and the tool's acts or actions with respect to the fab activity, in response to one or more commands, instruction sets, hardware or software commands, or other control-based directions of the controller.
More particularly, a process tool may involve a horizontal diffusion furnace scavenger system (also included within the term used herein as “furnace” and used specifically as “horizontal furnace”).
FIG. 1A depicts an example of a typical wafer 100 produced by a process tool, such as horizontal furnace, in an established process. In FIG. 1A, the wafer 100 has elements which may vary with respect to the type of process tooling and fab process undertaken in its manufacture, including a substrate 120 and a memory cell area 130. A memory cell often includes two or more field oxide areas (i.e., isolation regions) 110 which are often grown areas of oxide formed by a local oxidation of silicon (LOCOS) process.
The LOCOS process is in effect an isolation scheme commonly used in metal oxide semiconductors (MOS) and complementary MOS (CMOS) technology in which a thick pad of thermally grown SiO2 separates adjacent devices such as P-channel MOS and N-channel MOS transistors. Local oxidation is often accomplished by using silicon nitride to prevent oxidation of silicon in predetermined areas, and silicon is typically implanted between a silicon nitride region to form channel stops.
From FIG. 1A, the memory cell 130 is formed above an active area 140 of the substrate 120 and is situated typically between the adjacent field isolation regions 110. The memory cell 130 typically comprises a gate insulation layer 135 (i.e., tunnel oxide layer), a floating gate electrode 145 (often of polysilicon), a composite inter-poly insulation layer 150, and a control gate electrode 160 (often of polysilicon). In many implementations of the example of FIG. 1A, the insulation layer 150 is also known as an oxide-nitride-oxide (ONO) layer as it is often comprised of a layer of silicon dioxide 151, a layer of silicon nitride 152 and a layer of silicon dioxide 153, though other variations are also known.
From FIG. 1A, the thickness and dielectric constants of the floating gate electrode 135 and the layers of each of the ONO layer (i.e., 151, 152 and 153) may affect the overall performance of the memory cell and the associated integrated or electronic circuitry, depending on their thickness and formation details. Similarly there are also other characteristics of the memory cell related to physical structures, thickness, conductivity, uniformity, capacitance, band voltage, resistance, and growth impacts due to temperature and/or pressure during the deposition process, which may affect performance which directly results from a process tool's operation on the wafer (i.e., collectively “performance variables,” “performance variances” or “performance characteristics”).
In a traditional furnace or furnace bank, there may exist more than one furnace tube in which a predetermined number of furnace tubes perform a similar process. FIG. 1B depicts a typical eight-tube furnace bank arrangement 190.
By example, the furnace bank of FIB. 1B is a process tool having two four-furnace banks at 191a and 191b, totaling eight similar separate tubes (i.e., furnace tubes) (191a, 191b, 191c, 191d, 191e, 191f, 191g, and 191h), each arranged to perform a furnace-based activity on a wafer set in the fab process. In a typical arrangement 190, each tube is arranged to receive a set of silicon wafers (192a, 192b, 192c, 192d, 192e, 192f, 192g, and 192h) which are typically received by the respective tube of the arrangement 190. In FIG. 1B, by example, wafer set 192h is about to be received into the proper bay area of furnace tube 191h, while all other wafer sets have been properly positioned in their respective tube bay. At 193a, 193b, 193c, 193d, 193e, 193f, 193g, and 193h are controllers each of which controls its respective furnace tube along 194a or 194b. Both pressure and heat source are integral features of a typical furnace (not shown). Once the wafers are inserted into the their respective tubes, the wafers are acted upon in accordance with the designated process, and thereafter removed. Once removed, yield variations of the wafers may be determined and compared.
FIG. 2 depicts a typical horizontal diffusion furnace scavenger system 200 for a particular process. In FIG. 2, by example, the horizontal furnace 200 is designed to perform Diffusion/Atmospheric and Low Pressure Chemical Vapor Deposition (LPCVD) processing on predetermined wafers of a particular range of sizes. The Example configuration of FIG. 2 is referred to as a right-handed system, as determined in relation to the position of the furnace with regard to an operator. The horizontal furnace includes a load station at 210 in which wafers are loaded for travel into the furnace portion 220 of the horizontal furnace for processing. A gas cabinet provides associated gases for furnace processing at 230. A power system provides power and control logic to the system at 240. Operatively, once the wafers are fully processed, the wafers are removed from the furnace and returned to the load station.
FIG. 3 depicts a more detailed view of a load station 300 in a particular arrangement for loading wafers into an associated four-tube furnace bank (not shown). From FIG. 3, wafers depicted at 310 are being readied for loading into an associated furnace tube (not shown) of a furnace bank. Wafers 310 are situated on a furnace paddle 320 in a predetermined arrangement in relation to the associated furnace tube. A boat loader 330 is arranged with the furnace paddle to horizontally push or pull the furnace paddle with the wafers into or out of the associated furnace tube. The boat loader is mechanically and controllably arranged to traverse a predetermined portion of the load station into the associated furnace tube, generally close or reduce interface access between the loading station and the associated furnace tube by positioning a sealing door 340 in proximity to an interface near the furnace tube outer wall at 350, await completion of processing of loaded wafers, and in response to control logic (not shown), remove the processed wafers from the furnace into the loading station. The boat loader also includes a secondary door at 360. The process may be often repeated for further wafer processing.
Additionally, from FIG. 3, a boat loader 335, in association with a further furnace tube (not shown) of the furnace bank, has traversed its predetermined portion of the load station, reduced the interface access 370 between the loading station and the associated furnace tube by positioning its sealing door in proximity to an interface near the furnace tube outer wall. Further, to prevent particles on the wafers during the loading process, it is understood that a constant horizontal laminar flow from the load station into an external environment, such as a cleanroom, be provided to create filtered air inside the loading station.
FIG. 4 depicts detail of a further example of a furnace and scavenger system 400 for wafer fabrication. In FIG. 4, a boat loader assembly, controlled by a controller 411, is arranged with a boat loader 410, furnace paddle 415, a sealing door 420 and a quartz door 430 for providing wafers 440 into a furnace tube 450. As depicted, by example, in FIG. 4, the wafers 440 are completely inserted to a predetermined position within the furnace tube by the boat loader assembly. The scavenger area 460 exhausts gases from the furnace, resident in the area, and the gases are externally exhausted at 470 from the system, often by an external fan or exhausting system. Operationally, the controller 411 controls the loading and unloading of the wafers 440 into the furnace tube 450 by the boat loader assembly, resulting in a sealing gap 480 as between the sealing door 420 and the furnace/scavenger area 460.
FIG. 5 depicts a typical operational oxidation cycle 500 for wafer fabrication using a furnace system. From FIG. 5, a process is started at 510 in which wafers are first loaded onto a paddle arranged for loading at 520. The furnace system is often programmed for a specific processing recipe at 525 and the loaded wafers are inserted into a furnace tube by the boat loader assembly at 530. Once the wafers are completely inserted into the furnace tube, in accordance with the recipe, processing begins and predetermined temperatures are established by the furnace at 535.
Once temperatures reach a first established level, temperature ramping often occurs at 542 in which the furnace tube temperature is varied in accordance with a temperature cycle predetermined by the recipe, (e.g., 875-1200° C.). Further process gases (i.e., nitrogen, oxygen, etc.) are introduced at 544 in accordance with recipe and act upon the wafer at a predetermined time in the process cycle at a predetermined temperature. These two steps result in the creation of exhaust gases which are then removed from the process to an external environment by the scavenger system 540.
At a predetermined time, the process begins the final steps of completion where the gases cease flowing at 545 and the temperature of the furnace is reduced at 550. Once completed, the boat loader assembly returns to a load/unload position at 560 and the finished wafers, processed in accordance with the recipe, may be removed at 570. The boat loader assembly then may continue operations or stop operations at 580. At 580, the boat loader assembly is either readied for another wafer batch for processing at 585 and a process begins again at 510, or the boat loader assembly is not placed into further processing sequences at 590. The block at 544 depicts where the primary oxide growth period occurs during typical wafer fabrication processes.
In many implementations, the boat loaders are automatically controlled in their operation by a digital process controller (DPC) or similar. The boat loader assembly, operationally, is often speed-controlled and driven by a servo-styled motor to limit vibration as the boat loader traverses the predetermined path. In other implementations, the boat loaders are mechanically different than those depicted in the Figures, but comprise in one or another a sealing door, a paddle, and a mechanism for delivery of the wafers into a furnace area. Collectively, such implementations are referred to herein as “boat loaders.”
Unfortunately, variances in the yield (e.g., produced semiconductor or memory cell) often occur even with preprogrammed furnace systems, where variances in temperatures, pressures, and other processing variants occur thereby affecting the oxide characteristics of the yield. Some of the yield variances can be determined in the produced wafer's film thickness, stress, and dopant percentages, each of which is also directly associated with predictable comparative performances of the produced wafer. As many of these processes are automated and include high capacity productions, the variance resulting can produce sizeable yield variances which are not acceptable.
One attempted solution is to vary times for furnace oxidation sequences where the oxidation time is varied for the same single recipe, across furnaces. However, even with this approach, different oxidation times yield wafers having differing oxide characteristics as oxide results are directly dependent on processing characteristics resulting in different rates of growth. This attempted approach also does not account for variance due to environmental and other surrounding effects.
For instance, the traditional approaches are further limited by the programmed or fixed approach of the production process where dynamic factors (such as neighboring furnace tubes and systems, air flow patterns, and temperature effects of opened and closed systems proximate thereto) are not accounted for. As a result, processing characteristics are not effectively managed and dynamically controlled, resulting in yields having performance characteristics that are different than what had been desired.
Therefore, optimally producing high-quality products in a fabrication (i.e., “fab”) environment yielding oxide consistency in produced wafers, and fewer performance variances in process steps, is desired. Additionally, limiting such performance variances commonly across a set of equipment within furnace systems and fab environments, and improving consistency in yield output for similar-functioning but different process systems in a fab environment, is also needed. Further, it is highly is desired to be able to predictably coordinate differing line systems to develop consistency in process controls for oxide thickness control and particularly that of gate oxides.
The present invention, in accordance with its various implementations herein, addresses such needs.